1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically to a structure enabling fast row access of dynamic random access memory (DRAM).
2. Description of the Background Art
In a dynamic random access memory (hereinafter abbreviated as a DRAM), a memory cell includes an MOS transistor (an insulated gate type field effect transistor) and a capacitor. Thus, the dynamic random access memory is smaller in number of components of a memory cell and correspondingly smaller in cell area, as compared with an SRAM (Static Random Access Memory) whose memory cell requires four transistors and two load elements. Therefore, the DRAM is suited for a memory with a large storage capacity and widely used as a main storage in a data processing system.
In the DRAM, memory cell data is destructively read and the memory cell data is sensed, amplified and latched by a sense amplifier circuit. The destructively read memory cell data is restored by latch data of the sense amplifier circuit. A column selection is performed with the memory cell data latched by the sense amplifier circuit for data access (data writing or reading). Unlike the SRAM, in the DRAM, after a selected row is driven into a non-selected state, another row must be driven into a selected state in switching pages (row: corresponding to one word line). Thus, after a circuit (a row related circuit) for row selection is once set in a precharged state, another row must be selected. Consequently, an overhead in switching pages is relatively large and a row access (a time required from row selection to data reading) takes a long time.
To reduce the overhead in switching pages, a plurality of banks are provided, which are accessed in an interleaved manner. More specifically, during data access to one bank, a row of another bank is driven into a selected state. As soon as data access to the one bank is completed, successively, the selected row of another bank is accessed. Thus, the page switching is effectively hidden by the data access operation, whereby a penalty is not caused in page switching. Accordingly, for example, during data access in a page mode for fast data access, wait time of a processor such as a central processing unit (CPU) is eliminated in a data processing system and the performance of the system is improved.
A clock synchronous DRAM (SDRAM) has been widely used which performs data transfer in synchronization with a clock signal such as a system clock, to increase a data transfer speed.
FIG. 26A is a diagram showing an exemplary operation sequence in data reading in a conventional SDRAM. In the SDRAM, an operation mode is designated by a command COM.
Referring to FIG. 26A, in a cycle #A of a clock signal CLK, an active command ACT for driving a row into a selected state is applied. In the SDRAM, a plurality of banks are provided and the designation of a bank 0 is represented by the suffixed number of command ACT in FIG. 26A. Active command ACT0 triggers selection of a row (a word line) in bank 0 in accordance with a concurrently applied row address, and memory cell data connected to the selected row are amplified and latched by sense amplifier circuits.
In a clock cycle #B, a read command READ instructing data reading is applied. Then, a memory cell is selected in accordance with a concurrently applied column address and data of the selected memory cell is read. A prescribed period of time is required after application of the read command for column selection and before the selected memory cell data is actually read externally. This period of time is referred to as a column latency CL. FIG. 26A shows an exemplary data reading operation when column latency CL is 2.
When column latency CL (=2) is elapsed in accordance with read command READ that has been applied in clock cycle #B, data D0 and D1 are respectively read prior to rising edges of clock signals CLK in clock cycles #C and #D. The number of data consecutively read by one read command READ is referred to as a burst length BTLH. FIG. 26A represents the data reading operation when burst length BTLH is 2. Data which is in a definite state at the rising edge of clock signal CLK is transferred, so that an externally provided processor samples the data at the rising edge of clock signal CLK. A transfer speed of data D is determined by a frequency of clock signal CLK, and fast data transfer is enabled.
When a row other than that selected by active command ACT0 is to be accessed in the same bank, a precharge command PRE is applied in a clock cycle #E and bank 0 is brought back into a precharged state in the SDRAM. When a prescribed period of time is elapsed, active command ACT0 is again applied in a clock cycle #F, and another row is designated, which is then driven into the selected state.
A mode in which data is transferred in synchronization with one edge of clock signal CLK is referred to as an SDR (Single Data Rate) mode. The SDRAM essentially has an array structure similar to that of a DRAM though data is transferred in accordance with the clock signal. Accordingly, after the row is driven into the selected state and data of the selected memory cells are sensed, amplified and latched by the sense amplifier circuits, next read command READ can be applied.
The time required between operations of a circuit for row selection (a row related circuit) and a circuit for column selection (a column related circuit) is generally called an RASxe2x88x92CAS delay time tRCD. FIG. 26A relates to the case where delay time tRCD is 2 clock cycles by way of example. Accordingly, it takes 4 clock cycles after active command ACT is applied and before effective data is externally output. Further, a time generally equal to an RAS precharge time tRP is required after precharge command PRE is applied and before active command ACT is applied then. This is because row selection must be newly performed after an internal circuit is surely brought back to the precharged state.
Consequently, in consecutively accessing different rows in the same bank even if a plurality of banks are provided, the above described overhead is caused due to page switching. Thus, memory cell data cannot be transferred at a high speed and the performance of the system is decreased.
To achieve higher data transfer speed than in the SDR mode, an operation mode called a DDR mode is becoming popular. In the DDR mode, as shown in FIG. 26B, data is transferred in synchronization with rising and falling edges of clock signal CLK. Here, FIG. 26B represents an exemplary operation sequence in data reading when RASxe2x88x92CAS delay time tRCD and column latency CL are both 2 and burst length BTLH is 4. The DDR mode SDRAM has an internal structure which is substantially the same as that of the SDR mode SDRAM. Accordingly, 4 clock cycles are required after active command ACT0 is applied in clock cycle #A and before effective data is output. In the DDR mode, data can be transferred in synchronization with both of rising and falling edges of clock signal CLK, and data can be transferred at a higher speed than in the SDR mode. However, data are transferred every half-cycle of clock signal CLK. Thus, the DDR mode is inferior to the SDR mode in terms of an efficiency of a bus utilization. In the SDR mode when burst length BTLH is 4, data is transferred over 4 clock cycles. On the other hand, in the DDR mode when the burst length is 4, data is transferred only for 2 clock cycles and not transferred for the remaining clock cycle period.
FIG. 27 is a graph showing a relationship between an operation frequency and a bus utilization efficiency when transferring data in SDR and DDR modes. Burst length BTLH is 4 in each of the SDR and DDR modes. A transfer time of internal data is determined by the internal structure of the SDRAM, and column latency CL changes in accordance with the operation frequency. If the operation frequency increases to 125 MHz or 133 MHz in the SDR mode, column latency CL increases. Since data is not transferred during column latency CL, the bus utilization efficiency decreases to about 0.55. Here, in FIG. 27, the bus utilization efficiency relates to data transfer when the SDRAM is randomly accessed and accesses to the same bank and to different banks occur at the same probability.
In the DDR mode, data is transferred in synchronization with both of rising and falling edges of clock signal CLK. Thus, the data transfer operation per se is performed at a high speed, and the processor can transfer required data in a short period of time. However, RASxe2x80x94CAS delay time tRCD and RAS precharge time tRP are the same as in the SDR mode, and these are predetermined. If the operation frequency increases, the clock cycle number per time also increases. Accordingly, as the operation frequency increases, the clock cycle number corresponding to the overhead in page switching increases in the DDR mode, whereby the bus utilization efficiency decreases.
In the DDR mode, data is transferred in synchronization with both of rising and falling edges of clock signal CLK. Thus, although the processor can transfer required data in a short period of time, there is a period during which data is not transferred on the bus. During data transfer in the DDR mode, since the data transfer period is shorter than in the SDR mode, the bus utilization efficiency is further reduced. For example, the bus efficiency at the operation frequency of 100 MHz during data transfer in the DDR mode is for example a little more than 0.4, and the bus utilization efficiency is about 0.3 when the operation frequency is 125 MHz. At the operation frequency of 166 MHz or 200 MHz, the clock cycle number of each of column latency CL, RASxe2x88x92CAS delay time tRCD and RAS precharge time tRP increases, the number of clock cycles during which data is not transferred increases, and the bus utilization efficiency becomes a little more than about 0.2, which is about half that in the case of the operation frequency of 100 MHz.
Therefore, even when a plurality of banks are provided and data is transferred in a bank interleaved manner, data is randomly accessed, and if different rows in the same bank are consecutively accessed the overhead in page switching is more disadvantageously affected as the operation frequency increases, whereby the bus utilization efficiency is disadvantageously reduced.
An object of the present invention is to provide a semiconductor memory device capable of reducing a penalty in page (row) switching within the same bank.
Another object of the present invention is to provide a semiconductor memory device capable of preventing a reduction in bus utilization efficiency when the same bank is consecutively accessed.
The semiconductor memory device according to the present invention includes a plurality of memory cells arranged in a matrix, and a plurality of sense amplifier circuits arranged corresponding to columns for sensing, amplifying and latching data of memory cells of the corresponding columns when activated. The plurality of sense amplifier circuits are divided into a plurality of groups.
The semiconductor memory device according to the present invention further includes connection circuitry responsive to a row selection designation and a sense amplifier group designation for separating a sense amplifier circuit of the designated sense amplifier group and a corresponding column when a prescribed period of time is elapsed after the row selection designation is applied. The prescribed period of time includes a period in which data of memory cells of the selected row is transmitted to the corresponding sense amplifier circuits.
The semiconductor memory device according to the present invention further includes sense control circuitry for activating sense amplifier circuits of the sense amplifier group designated by the sense amplifier group designation when the prescribed period of time is elapsed.
A semiconductor memory device according to another aspect of the present invention includes a memory array including a plurality of memory cells arranged in rows and columns, and a plurality of sense amplifiers arranged corresponding to the columns of the memory array for sensing, amplifying and latching memory cell data of the corresponding columns when activated. A plurality of sense amplifier circuits are provided corresponding to the columns. The stored data of a memory cell of the memory array can be sensed by any of a plurality of sense amplifier circuits of the corresponding column.
Provision of the plurality of sense amplifier circuits corresponding to each column enables memory cell data of different rows to be retained in the corresponding sense amplifier circuits for each column. Accordingly, with the sense amplifier circuits and the corresponding columns isolated, memory cell data of the different row can be sensed, amplified and latched by another sense amplifier circuit while accessing one sense amplifier circuit. Thus, by accessing the sense amplifier circuit with each column and an associated sense amplifier circuit isolated, memory cell data of different rows can consecutively be accessed, whereby a penalty in page switching in the same bank can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.